1. Field of the Invention
The invention relates generally to a method of manufacturing a copper metal wiring in a semiconductor device. More particularly, the present invention relates to a method of manufacturing a copper metal wiring in a semiconductor device capable of increasing the burial characteristic of copper (Cu) at the portion of holes having a small size and an increased aspect ratio, when forming a metal wiring by depositing Cu by chemically enhanced chemical vapor deposition (hereinafter called xe2x80x9cCECVDxe2x80x9d) method.
2. Description of the Prior Art
The performance of next-generation semiconductor devices is rapidly increasing. Thus, it accordingly causes reduction in the size of the contact and steep inclination of the aspect ratio. Thus, when forming a metal wiring, good contact burial characteristic and step coverage are required.
A method of forming a metal wiring in a semiconductor device employs a method by which a thin titanium (Ti) film is deposited and then aluminum (Al) is deposited by a physical vapor deposition (hereinafter called xe2x80x9cPVDxe2x80x9d) method or a chemical vapor deposition (hereinafter called xe2x80x9cCVDxe2x80x9d) method, or a method by which thin tantalum (Ta) or tantalum nitride (TaN) film as a diffusion prevention film is formed by a PVD method and Cu is then deposited by an electroplating method. The former method, however, has a problem when applied to next-generation high-performance semiconductor devices since Al has a higher resistance than Cu. On the other hand, the latter method has a limited burial characteristic of Cu due to rapid reduction in the size of the contact and increased aspect ratio. Also, as the tantalum nitride film used as a diffusion prevention film against Cu has a high resistance compared to Al to which the diffusion prevention film is not applied, there is a problem that a very thin film is required. As such, applying a copper wiring using aluminum wiring and electro-plating to next-generation semiconductor devices causes several problems.
In order to solve these problems, a study has been made on a method in which CVD method is applied in deposition of a copper wiring. This method, however, has a limitation in a bulk filling due to low deposition speed.
Recently, a study has been made on a method of depositing a thin copper film using a metal organic chemical vapor deposition (hereinafter called xe2x80x9cMOCVDxe2x80x9d) method using a chemical enhancer such as iodine (I) catalyst. The MOCVD method using this a chemical enhancer is referred to as the chemically enhanced chemical vapor deposition (hereinafter called xe2x80x9cCECVDxe2x80x9d) method. In the CECVD method, however, as the chemical enhancer is distributed on the entire damascene structure, there is a problem in that voids or seams are generated at the bottom of the hole having a smaller size and an increased aspect ratio during a subsequent copper deposition process.
The present invention to provide a method of manufacturing a copper metal wiring in a semiconductor device by which a diffusion prevention film is formed, a chemical enhancer treatment is performed and a chemical enhancer layer is then left over at the bottom of a hole, so that the growth rate of copper at the bottom of the hole can be increased when depositing copper using a subsequent copper precursor, thus preventing generation of voids or seams.
A method of manufacturing a copper metal wiring in a semiconductor device according to the present invention comprises forming an interlayer insulating film on a semiconductor substrate in which an underlying structure is formed; forming a damascene pattern by patterning a given region of the interlayer insulating film; performing a cleaning process, and then forming a diffusion barrier layer on the entire structure including the damascene pattern; forming a chemical enhancer layer on the diffusion barrier layer by performing a chemical enhancer treatment; leaving the chemical enhancer layer only at a contact hole of the damascene pattern by performing a spin rinsing process and a warm annealing process; sequentially forming first and second copper layers on the entire structure in which the chemical enhancer layer remains; and forming a copper metal wiring within the damascene pattern.